1. Field of the Invention
The present invention relates to a gate driving circuit and a display device having the gate driving circuit. More particularly, the present invention relates to a gate driving circuit that drives a gate line and a display device having the gate driving circuit.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) includes an LCD panel displaying an image by using the light transmissivity of liquid crystal, and a backlight assembly disposed behind the LCD panel to supply light to and through the LCD panel.
The LCD further includes a gate driving circuit connected to a plurality of gate lines and a data driving circuit connected to a plurality of data lines. The plurality of data lines cross the gate lines at the plurality of pixels, each pixel respectively connected to one of the gate lines and to one of the data lines. The gate driving circuit outputs a gate signal to one of the gate lines at a time, and sequentially to all of the gate lines. The data driving circuit outputs a data signal to all of the data lines. The gate driving circuit and the data gate driving circuit are formed in an in integrated circuit, usually formed on a silicon chip, typically mounted on the LCD panel.
Recently, in order to reduce the size of an LCD and to simplify the manufacture of the LCD, a process in which the gate driving circuit is integrated in an amorphous silicon layer deposited on a display substrate has been developed. When the gate driving circuit integrated in the integrated circuit formed on the display substrate is driven in high temperature conditions, visible noise defects such as ripples may be generated during a “gate-OFF signal” period.
Moreover, as LCD panels become dimensionally larger, the resistive and capacitative loads of the lines in the LCD panels are increasing so that resistive-capacitive (RC) delay is increased. However, as the number of gate lines increases with increasing resolution pulse widths of gate signals are decreasing. When pulse widths of gate signals are decreased, the charging time for charging a data voltage on a line is decreased, so that a charging rate of the data voltage may be reduced.